Design flow for Globally Asynchronous Locally Synchronous Systems using Conventional Synchronous Design Tools

– We propose a design flow for Globally Asynchronous Locally Synchronous systems, which can be used by designers without prior knowledge of asynchronous circuits. The design flow uses conventional synchronous design tools and we have developed a tool to generate and handle the asynchronous circuits in the flow. The design flow starts with high-level model of the system behavior and proceeds down to an implementation in an FPGA or an ASIC. The generated asynchronous wrappers can produce its own clock signal using an internal oscillator or use an external oscillator. An external oscillator can be used if a specific clock frequency must be obtained. The proposed design flow is currently used for implementing a physical layer for a wireless LAN. Key-Words: – GALS, Design flow, Asynchronous, FPGA, Simulink